Hardware Performance Analysis of N-bit CLA on FPGA and Programmable SoC

Carry Look Ahead Adders (CLA) minimize duration opposed with various adders through transmitting carry preceding the total output, which leads to better results. They increase efficiency by lowering the duration it takes to figure out carry bits. In comparison, the ripple carry adder calculates the carry bit inside its total bit, as well as every single bit needs to wait till the previous carry bit has been computed before considering both the outcome and extra bits. This paper focuses on simulation and its hardware implementation for N-bit CLA with comparison for different bits for their time delay, area and power performance. The simulation was done using AMD-Xilinx ISE 14.7 tool for Spartan 3E based FPGA and Zynq 7000 PSoC using Verilog HDL and the performance improvements in propagating the carry and generating the sum was observed when compared with the other traditional CLA implementations. Finally, we were able to demonstrate the fact that the proposed generic CLA implementations were more efficient among similar existing in the research literatures.