Remote field-programmable gate array laboratory for signal acquisition and design verification
Journal article
Authors/Editors
Strategic Research Themes
Publication Details
Author list: Rithea Sum, Watcharapan Suwansantisuk, Pinit Kumhom
Publisher: Institute of Advanced Engineering and Science
Publication year: 2024
Journal acronym: IJECE
Volume number: 14
Issue number: 2
Start page: 2344
End page: 2360
Number of pages: 17
ISSN: 2088-8708
eISSN: 2722-2578
URL: https://ijece.iaescore.com/index.php/IJECE/article/view/34095
Languages: English-United States (EN-US)
Abstract
A remote laboratory utilizing field-programmable gate array (FPGA) technologies enhances students’ learning experience anywhere and anytime in embedded system design. Existing remote laboratories prioritize hardware access and visual feedback for observing board behavior after programming, neglecting comprehensive debugging tools to resolve errors that require internal signal acquisition. This paper proposes a novel remote embedded-system design approach targeting FPGA technologies that are fully interactive via a web-based platform. Our solution provides FPGA board access and debugging capabilities beyond the visual feedback provided by existing remote laboratories. We implemented a lab module that allows users to seamlessly incorporate into their FPGA design. The module minimizes hardware resource utilization while enabling the acquisition of a large number of data samples from the signal during the experiments by adaptively compressing the signal prior to data transmission. The results demonstrate an average compression ratio of 2.90 across three benchmark signals, indicating efficient signal acquisition and effective debugging and analysis. This method allows users to acquire more data samples than conventional methods. The proposed lab allows students to remotely test and debug their designs, bridging the gap between theory and practice in embedded system design.
Keywords
No matching items found.