Linearization of CMOS CCCII with optimal design via geometric programming
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Publication Details
Author list: Chaisricharoen R., Chipipop B., Chamnongthai K., Higuchi K., Sirinaovakul B.
Publisher: Hindawi
Publication year: 2009
Start page: 1492
End page: 1497
Number of pages: 6
ISBN: 9784907764333
eISSN: 1745-4557
Languages: English-Great Britain (EN-GB)
Abstract
The mixed translinear loop, serving as the input stage of a CMOS CCCII, is analyzed in large signal method to examine the linearity condition, which is simply the matching between NMOS and PMOS loop components. Example configurations, providing linear and nonlinear V-I characteristic of input voltage and current, are simulated in the HSPICE based on the AMS's 0.35μ CMOS process. The results verify the necessity of matching condition in designing a linear CMOS CCCII. To obtain an optimized design, the geometric programming is utilized based on attained perceptions. A sample requirement, also based on the AMS's 0.35μ CMOS process, is globally optimized. The obtained solution is simulated in the HSPICE to verify the performances, which are satisfying the requirement quite well. © 2009 SICE.
Keywords
Geometric programming, Linear
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