Development of a flexible hardware core for genetic algorithm
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Publication Details
Author list: Pimery J., Kumhom P.
Publisher: Hindawi
Publication year: 2009
Volume number: 1
Start page: 867
End page: 870
Number of pages: 4
ISBN: 9781424447541
ISSN: 0146-9428
eISSN: 1745-4557
Languages: English-Great Britain (EN-GB)
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Abstract
A hardware design for genetic algorithm (GA) can implement only one specific cost function of a problem at a time. Actually, different GA applications require different GA hardware architecture. The development of a flexible very-largescale integration (VLSI) for GA has been proposed in this paper. For the hardware architecture, we has develop on a random number generator (RNG), crossover, and mutation based on flexibility structure. This structure can dynamically perform to the 3 types chromosome encoding: binary encoding, real-value encoding, and integer encoding. The overall structures has been designed and synthesized by VHDL (VHSIC hardware description language), simulation by ModelSim program, and then implemented on FPGAs (Field programmable gate arrays). This hardware architecture that our design work very well flexible for the 3 groups problem examples: combinatorial optimization problems, function optimal problems, and part planning optimization problems. ฉ2009 IEEE.
Keywords
Chromosome encoding, Field programmable gate arrays(FPGAs), ModelSim, VHSIC hardware description language(VHDL)
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