A balanced differential-pair CMOS CCCII with negative intrinsic resistance

Conference proceedings article

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Author list: Chipipop B., Chaisricharoen R., Sirinaovakul B.

Publisher: Hindawi

Publication year: 2009

ISBN: 9781424437863

ISSN: 0146-9428

eISSN: 1745-4557

URL: https://www.scopus.com/inward/record.uri?eid=2-s2.0-70449470111&doi=10.1109%2fISSCS.2009.5206222&partnerID=40&md5=f0ba3a5e2cf0ebaabf62a2e025ede2ac

Languages: English-Great Britain (EN-GB)

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Abstract

A novel structure, based on balanced differential-pair, is proposed to implement the CMOS CCCII with negative intrinsic resistance at port X. HSPICE simulations, based on the AMS's 0.35μ CMOS process, are conducted, which certainly confirm the occurrence of negative resistance. To demonstrate its capability, a two-phase current-mode oscillator is synthesized based on two lossless integrators. As little error in oscillated frequency is observed, the proposed structure earns its place as one of the attractive negative-resistance simulators. © 2009 IEEE.

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