Trimming lithography part I: The alternative technology for sub-resolution and sub-wavelength patterning

Conference proceedings article

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Publication Details

Author list: Atthi N., Sriklat A., Jeamsaksiri W., Hruanun C., Poyai A., Silapunt R.

Publisher: Hindawi

Publication year: 2011

Start page: 42

End page: 45

Number of pages: 4

ISBN: 9781457704246

ISSN: 0146-9428

eISSN: 1745-4557

URL: https://www.scopus.com/inward/record.uri?eid=2-s2.0-79961225582&doi=10.1109%2fECTICON.2011.5947766&partnerID=40&md5=0ef4b2e4fb9051c9b3968d422377d8f5

Languages: English-Great Britain (EN-GB)

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Abstract

Lithography is the key technology to scale down a size of integrated circuits that will increase the performance of an electronics device (smaller, faster, cheaper, and low power consumption). There are many lithographic techniques which can produce a nanometer feature size. However, the cost for equipment and mask for those techniques is extremely high. Based on this limitation, this paper introduces an alternative patterning technique called Trimming lithography to produce sub-resolution and sub-wavelength features. The results show that as small as 0.18 μm photoresist linewidth can be produced using the 0.8 μm pattern on a conventional binary mask. The trimming lithography can thus be one of the candidates for future lithography. © 2011 IEEE.

Keywords

Moore's law, Next generation lithography, Pattern shrinkage, Sub-resolution patterning, Trimming lithography