A hardware implementation for real-time lane detection using high-level synthesis

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Publication Details

Author list: Khongprasongsiri C., Kumhom P., Suwansantisuk W., Chotikawanid T., Chumpol S., Ikura M.

Publisher: Hindawi

Publication year: 2018

Start page: 1

End page: 4

Number of pages: 4

ISBN: 9781538626153

ISSN: 0146-9428

eISSN: 1745-4557

URL: https://www.scopus.com/inward/record.uri?eid=2-s2.0-85048754741&doi=10.1109%2fIWAIT.2018.8369730&partnerID=40&md5=feaadfc62aa6889b478ae94d9204469e

Languages: English-Great Britain (EN-GB)

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Abstract

Lane detection plays an important role in advanced driving assistance systems (ADAS). In this paper, a hardware implementation of a real-time lane detection is developed using the Xilinx's Zynq-7000 APSoC platform. The proposed algorithm of lane detection uses the Hough transform, which is necessary in our implementation but causes a performance bottleneck. The overlapping pipeline architecture is adopted so that latency and stage memory are minimal. While running at 100 MHz, the implemented hardware can achieve a speed performance of 130 frames per second, for a frame resolution of 480ื270. Video streams of actual street conditions are used to test the system. From the test results, accuracy of lane detection is found to be satisfactory. ฉ 2018 IEEE.

Keywords

advanced driving assistance system, high-level synthesis, pipeline architecture