Implementation of zero-ripple line current induction cooker using class-d current-source resonant inverter with parallel-load network parameters under large-signal excitation

บทความในวารสาร

ผู้เขียน/บรรณาธิการ

กลุ่มสาขาการวิจัยเชิงกลยุทธ์

ไม่พบข้อมูลที่เกี่ยวข้อง

รายละเอียดสำหรับงานพิมพ์

รายชื่อผู้แต่ง: Ekkaravarodome C., Thounthong P., Jirasereeamornkul K.

ผู้เผยแพร่: Korean Institute of Electrical Engineers

ปีที่เผยแพร่ (ค.ศ.): 2018

Volume number: 13

Issue number: 3

หน้าแรก: 1251

หน้าสุดท้าย: 1264

จำนวนหน้า: 14

นอก: 1975-0102

eISSN: 1975-0102

URL: https://www.scopus.com/inward/record.uri?eid=2-s2.0-85045443774&doi=10.5370%2fJEET.2018.13.3.1251&partnerID=40&md5=652ac9b64a26802e493fc0f53a77a94f

ภาษา: English-Great Britain (EN-GB)

ดูในเว็บของวิทยาศาสตร์ | ดูบนเว็บไซต์ของสำนักพิมพ์ | บทความในเว็บของวิทยาศาสตร์

บทคัดย่อ

The systematic and effective design method of a Class-D current-source resonant inverter for use in an induction cooker with zero-ripple line current is presented. The design procedure is based on the principle of the Class-D current-source resonant inverter with a simplified load network model that is a parallel equivalent circuit. An induction load characterization is obtained from a large-signal excitation test-bench based on parallel load network, which is the key to an accurate design for the induction cooker system. Accordingly, the proposed scheme provides a systematic, precise, and feasible solution than the existing design method based on series-parallel load network under low-signal excitation. Moreover, a zero-ripple condition of utility-line input current is naturally preserved without any extra circuit or control. Meanwhile, a differential-mode input electromagnetic interference (EMI) filter can be eliminated, high power quality in utility-line can be obtained, and a standard-recovery diode of bridge-rectifier can be employed. The step-by-step design procedure explained with design example. The devices stress and power loss analysis of induction cooker with a parallel load network under large-signal excitation are described. A 2,500-W laboratory prototype was developed for 220-Vrms/50-Hz utility-line to verify the theoretical analysis. An efficiency of the prototype is 96% at full load. ฉ The Korean Institute of Electrical Engineers.

คำสำคัญ

Class-D current-source resonant inverter, Zero-ripple line current